Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
To implement a circuit design using an FPGA, the design is synthesized to produce a logical representation, which is then mapped onto programmable logic blocks, placed within the FPGA, and routed using the programmable fabric. The place and route phases of implementing a circuit design involve generating a layout of the circuit elements on the FPGA and defining the signal lines (routing resources) that connect the elements.
Presently, the design tools used to implement a circuit design perform their tasks on the user's design without regard to the specifics of the design or to the execution history of the design tools. For example, if a place-and-route tool processes a design to produce a result, all subsequent executions by the place-and-route tool for the same design will produce the same result both in terms of the quality of the result, as well as the execution time taken to achieve the result. Typically, in a design cycle a user will execute the implementation tools several times on different versions of the design. Each successive version may only be slightly different. However, the implementation tools deal with these versions as if they were completely independent and distinct designs despite the fact that these versions may only be slightly different. As such, the results and run-time of the implementation tools of a slightly different version do not leverage the results of the previous version and, therefore, may not show any significant improvement in the quality of results or execution time from version to version.
Accordingly, there exists a need in the art for a method and apparatus for implementing a circuit design for an integrated circuit that takes less time to run while providing improved results.